发明名称 SYSTEM FOR CONTROLLING PRE-CHARGE LEVEL IN MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a system for controlling the pre-charge level of a dual bit memory cell in a memory cell. <P>SOLUTION: The system includes an apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit actuates to maintain the same voltage level on the first and second terminals. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2003323796(A) 申请公布日期 2003.11.14
申请号 JP20030122155 申请日期 2003.04.25
申请人 FUJITSU LTD 发明人 YAMADA SHIGEKAZU
分类号 G11C16/06;G11C7/12;G11C16/02;(IPC1-7):G11C16/06 主分类号 G11C16/06
代理机构 代理人
主权项
地址