发明名称 |
Memory circuit testing system, semiconductor device, and memory testing method |
摘要 |
A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.
|
申请公布号 |
US2003212925(A1) |
申请公布日期 |
2003.11.13 |
申请号 |
US20030455304 |
申请日期 |
2003.06.06 |
申请人 |
FUJITSU LIMITED |
发明人 |
OGURA KIYONORI;MURASE YASUNORI |
分类号 |
G11C11/406;G11C29/02;(IPC1-7):H04B1/74 |
主分类号 |
G11C11/406 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|