| 摘要 |
Calculation circuit for calculating a sampling phase error for a decision feedback clock phase regulation circuit, having a first delay element chain (31), which has a plurality of serially connected delay elements, for delaying a digital estimate âK of a decision device; a second delay element chain (32), which has a plurality of serially connected delay elements, for delaying an equalized signal (zk, ek); a multiplier array (33) which consists of multipliers arranged in matrix form and which multiplies the undelayed digital estimate aK and the delayed estimates of all the delay elements of the first delay element chain (31) by the equalized signal (zk, ek) and the delayed output signals of all the delay elements of the second delay element chain (32) in order to generate product signals; a weighting circuit (39) which multiplies the product signals generated by the multiplier array by adjustable weighting factors (bij); and having an adder (41) which adds the product signals weighted by the weighting circuit (39) to the sampling phase error signal (Vk) which is output via a signal output (24) of the calculation circuit (1).
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