| 摘要 |
A serial data communication machine includes a counter for counting a reference clock and a shift register for receiving incoming and outgoing data. Every time the counter counts the reference clock certain times, which is equal to a first integer determined in accordance with a ratio of a reference clock frequency to a transfer rate, the data stored in the shift register are shifted such that the data are transmitted and received at a rate substantially equal to the transfer rate. The communication machine also includes a clock correction unit. Every time the reference clock is generated certain times, which is equal to a second integer determined in accordance with a difference between the above mentioned ratio and the first integer, the clock correction unit temporarily hinders passage of the reference clock to the counter. Even if one bit time is not a multiple of the reference clock, the communication machine can transfer the data at high speed without increasing the reference clock frequency.
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