| 摘要 |
A microprocessor capable of supplying a stable internal clock signal even at the time of mode switching. A clock supply control circuit is connected between a clock generator circuit (PLL) and synchronous circuits (integer unit, instruction cache, data cache). The clock supply control circuit includes a bus interface unit, OR gates, and first and second delay circuits. With this microprocessor, when operations of the synchronous circuits are to be started, the supply of the internal clock signal from the PLL to the synchronous circuits is started in a time-staggered manner in order of the integer unit, the instruction cache, and the data cache. This serves to suppress noise at the start of operation and to keep the PLL locked, and as a result, the supply of the internal clock signal can be stabilized even at the time of mode switching.
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