发明名称 |
Emulating multiple bus used within a data processing system |
摘要 |
A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.
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申请公布号 |
US2003212968(A1) |
申请公布日期 |
2003.11.13 |
申请号 |
US20020142148 |
申请日期 |
2002.05.10 |
申请人 |
NIGHTINGALE ANDREW MARK;MACE TIMOTHY CHARLES |
发明人 |
NIGHTINGALE ANDREW MARK;MACE TIMOTHY CHARLES |
分类号 |
G06F11/26;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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