MEMORY REGION BASED DATA PRE-FETCHING

摘要

As microprocessor speeds increase, processor performance is more and more affected by data access operations. When a processor, in operation, needs to await data due to slow data retrieval times, this is termed a processor stall and, in quantitative terms is referred to as processor stall cycles. As would be anticipated, pre-fetching of data from RAM memory is performed to reduce processor stall cycles, where a goal of pre-fetching in a processor-based system is to reduce a processing time penalty incurred during the processor stall cycle. Providing a combined solution of hardware and software directed pre-fetching is the most advantageous since: instruction bandwidth is not compromised, by limiting an amount of additional instructions in a program stream, and an additional amount of hardware resources is minimized. Instead of trying to detect regularity in memory references by hardware or software, as is taught in the prior art, the hardware and software directed pre-fetching technique is performed without explicit pre-fetch instructions utilized within the program stream and occupies a minimal amount of additional chip area. In order to minimize instruction bandwidth of the processor, the software and hardware directed pre-fetching approach uses additional registers located at an architectural level of the processor in order to specify pre-fetch regions, and a respective stride to be used for each of the regions. Advantageously, the impact to the instruction bandwidth of processing of instructions by the processor is limited to those additional instructions contained within the application that are required to set these registers. Where a frequency of pre-fetches is controlled using a spacing of memory access instructions contained within the application.