| 摘要 |
<p>A method of isolating adjacent transistors in CMOS devices having strained silicon (12) and silicon germanium alloy (11) layers is disclosed. A semiconductor device combines in a single CMOS device the advantages of surface n-channel strained silicon MOSFETs with those of buried p-channel compressively strained silicon-germanium MOSFETs, without the need to compromise the performance of either type of transistor. By forming electrically insulating barrier regions (8) before formation of the strained silicon layer (12), this avoids the problem of high temperature processing steps causing germanium to diffuse from layer (11) into the channels of transistors in layer (12) and thereby degrading the performance of the n-channel transistors formed by the method.</p> |
