发明名称 |
Multilayered wiring structure and method of manufacturing the same |
摘要 |
A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed. <IMAGE> |
申请公布号 |
EP0989610(A3) |
申请公布日期 |
2003.11.12 |
申请号 |
EP19990118900 |
申请日期 |
1999.09.24 |
申请人 |
NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.;FUCHIGAMI MICRO CO.,LTD. |
发明人 |
HIRASAWA, KOKI;ONO, TERUO |
分类号 |
H01L21/48;H01L23/12;H01L23/498;H01L23/538;H05K1/05;H05K3/42;H05K3/44;H05K3/46;(IPC1-7):H01L23/538 |
主分类号 |
H01L21/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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