发明名称 Digital to analog converter, delay-locked loop, memory device and counting method
摘要 <p>A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling. &lt;IMAGE&gt;</p>
申请公布号 EP1361661(A2) 申请公布日期 2003.11.12
申请号 EP20030001762 申请日期 2003.01.28
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHUNG,IN-YOUNG
分类号 H03M1/68;G11C7/16;G11C7/22;H03L7/081;H03L7/089;H03M1/06;H03M1/08;H03M1/66;H03M1/74;H03M7/00;(IPC1-7):H03M1/06 主分类号 H03M1/68
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