发明名称 |
Interface scheme for connecting a fixed circuitry block to a programmable logic core |
摘要 |
A method and architecture for providing signal paths between a programmable logic core and a fixed function core comprising the steps of (a) coupling one or more first signals between the fixed function core and an interface block configured to couple the fixed function core and the programmable logic core and (b) coupling one or more second signals between the interface block and the programmable logic core.
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申请公布号 |
US6646466(B1) |
申请公布日期 |
2003.11.11 |
申请号 |
US20010011936 |
申请日期 |
2001.12.05 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
COPPOLA ALAN J.;STANLEY JOEL;WILTON STEVEN J. E. |
分类号 |
H03K19/177;(IPC1-7):H03K7/38 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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