TWO-WAY EXAMINING FRAME SYNCHRONIZATION CIRCUIT

摘要

A frame synchronization circuit is disclosed, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system. The frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code, and a data loss and data insertion period judgement circuit which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.