发明名称 |
Data transfer control device, semiconductor memory device and electronic information apparatus |
摘要 |
A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.
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申请公布号 |
US6646947(B2) |
申请公布日期 |
2003.11.11 |
申请号 |
US20020184133 |
申请日期 |
2002.06.26 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
FUKUI HARUYASU;SUMITANI KEN;MORI YASUMICHI |
分类号 |
G06F12/02;G06F12/00;G06F13/28;(IPC1-7):G11C7/00 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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