| 摘要 |
An automated method of improving an integrated circuit layout comprises the steps of providing representation of the layout, identifying defect-susceptible portions thereof, and changing the geometry of at least one circuit element in each identified portion. Beneficial modifications that can be performed according to the invention include the addition of redundant vias, increasing the overlap around vias, lengthening polysilicon gate extensions, finding extra material critical area, finding pinhole critical area, finding missing material critical area, notch removal, visualization of defect sensitivity using a probability map and increasing the separation between neighboring polygons, preferably representing tracks. |
