| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a packet processing apparatus capable of applying processing to packet data needing numbers of processing steps more properly than a conventional packet processing apparatus. <P>SOLUTION: The packet processing apparatus includes: a processor block, wherein a plurality of packet access registers are connected in series in a multi- stage and packet data are sequentially transmitted between a plurality of the processors, including a plurality of the processors each having the packet access register with a shift register structure and executing a program for processing the packet data shifted in the packet access register by a prescribed number of steps; a means for transmitting takeover information required for taking over and executing processing for the packet data, executed by one processor, and going to be executed by a takeover destination processor existing at a post-stage from the next stage of the one processor, from the one processor to the takeover destination processor in conformity with the input of the packet data to the takeover destination processor. <P>COPYRIGHT: (C)2004,JPO</p> |
