| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce circuit scale and power consumption in a pipeline processor. <P>SOLUTION: A latch 105 is disposed between a first data processing part 102 and a second data processing part 103. When a processor is operated with a high clock frequency, a latch pulse synchronizing with a clock is inputted to the latch 105, and the output of the first data processing part 102 is held. Therefore, data processing parts 102 and 103 are successively operated in parallel, and high speed instruction code execution processing is operated as pipeline processing. When the processor is operated with a low clock frequency, continuous H level control signals are inputted to the latch 105. Therefore, the data processing parts 102 and 103 are operated as one processing stage without using any bypass circuit or selector. <P>COPYRIGHT: (C)2004,JPO |
