发明名称 |
High area efficient data line architecture |
摘要 |
A hierarchical bit line selection circuit is connected between a plurality of pairs of bit lines of a plurality of sub-arrays of a random access memory and a data line sense amplifier. The bit line selection circuit has a bit line selector circuit to selectively couple one pair of bit lines of the plurality of bit lines of each sub-array to the pair of local data lines. The bit line selection circuit further has a local data line selector circuit to select one of a plurality of pairs of local data lines to be connected to a pair main data lines that are connected to the inputs of the data line sense amplifier. The memory cell sub-arrays are folded in placement with the main data line switches to reduce data access time.
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申请公布号 |
US2003206479(A1) |
申请公布日期 |
2003.11.06 |
申请号 |
US20030387595 |
申请日期 |
2003.03.14 |
申请人 |
SHIAH CHUN;YUAN DER-MIN;WANG MING-HUNG;SHEN CHIUN-CHI |
发明人 |
SHIAH CHUN;YUAN DER-MIN;WANG MING-HUNG;SHEN CHIUN-CHI |
分类号 |
G11C7/18;G11C8/10;(IPC1-7):G11C8/12 |
主分类号 |
G11C7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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