发明名称 |
DIGITAL SIGNAL CODING/DECODING APPARATUS |
摘要 |
<p>In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset. <IMAGE></p> |
申请公布号 |
CA2756676(A1) |
申请公布日期 |
2003.11.06 |
申请号 |
CA20032756676 |
申请日期 |
2003.04.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SEKIGUCHI, SHUNICHI;YAMADA, YOSHIHISA;ASAI, KOHTARO |
分类号 |
H03M7/40;G06T9/00;H04N7/24;H04N7/50;H04N7/52;H04N19/00;H04N19/105;H04N19/13;H04N19/174;H04N19/46;H04N19/51;H04N19/625;H04N19/70;H04N19/91 |
主分类号 |
H03M7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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