发明名称 INPUT-PATTERN FEEDER AND INSPECTION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten the time required for observing a waveform and to suppress the failure analytical time. SOLUTION: When an internal circuit waveform of a semiconductor device is observed, a reset circuit 19 used to output a reset signal 21 for setting a pseudorandom pattern generator 12 to an initial value is added to the pattern generator 12 so as to correspond to a specific output, a cycle of a random pattern to be output is shortened, the time required for observing the waveform is shortened, and the failure analytical time is suppressed. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003315426(A) 申请公布日期 2003.11.06
申请号 JP20020121535 申请日期 2002.04.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIMURA TAKASHI;YOSHIMURA MASAYOSHI
分类号 G01R31/3183;G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/318 主分类号 G01R31/3183
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