| 摘要 |
The present invention relates to a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2). In particular, the clock generator circuit according to the invention comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) supplying clock signals (ck<1>,ck<2>,ck<3>,ck<4>) on a plurality of outputs (07), each of the primary inverters (15) having an input terminal (I15) connected to an output terminal (016) of a secondary inverter (16) preceding it in the loop (14), and to the ground voltage reference (GND) through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (015) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the output terminals (07) The invention also concerns a charge pump circuit and a phase generator (9) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2) as well as to a three-terminal capacitor.
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