| 摘要 |
A memory subsystem and a method for accessing a memory subsystem are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a memory controller. The memory controller is capable of waiting to generate a memory clock signal for each of the SDRAM memory modules until a valid window for a control signal and an address signal, generating the memory clock signals during the valid window, and generating the control and address signals. The method comprises: waiting for a valid window for a control signal and a command signal; generating a memory clock during the valid window; and generating the control signal and the command signal a predetermined period of time after generating the memory clock signal.
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