发明名称 Method and system for efficient cache memory updating with a least recently used (LRU) protocol
摘要 A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, there is an update of the least recently used status for the cache entries with reference to the memory requests.
申请公布号 US6643742(B1) 申请公布日期 2003.11.04
申请号 US20000528748 申请日期 2000.03.20
申请人 INTEL CORPORATION 发明人 VIDWANS ROHIT;BEAVENS JAMES A.
分类号 G06F12/12;(IPC1-7):G06F12/00 主分类号 G06F12/12
代理机构 代理人
主权项
地址