Digital circuit, LSI including the same and method for removing noise

摘要

A digital circuit, which avoids problems in LSIs including erroneous operation even when noise is superposed on a clock signal, is provided. A frequency divider divides the frequency of a first clock signal to generate a raw clock signal. A first flip-flop synchronizes the raw clock signal with a second clock signal. A second flip-flop synchronizes an output signal of the first flip-flop with the first clock signal and outputs the synchronized signal as a reproduced clock signal.