Packet command driving type memory device

摘要

The present invention relates to a packet command driving type memory device, comprises a first signal generating means for receiving a signal being generated from a register and generating a domain signal of certain bit; a second and a third signal generating means for generating a first and a second control signal for loading data; a fourth and a fifth signal generating means for generating a third and a fourth control signal for reading data from a core block; a data output shift part for shifting the data read from the core block according to the first and the second control signal generated from the second and a third signal generating means and a clock signal, delaying the shifted data by a certain time according to the domain signal generated from the first signal generating means according to each domain and compensating for a data output time and outputting it.