发明名称 |
Reducing clock skew in clock gating circuits |
摘要 |
One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.
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申请公布号 |
US6643829(B1) |
申请公布日期 |
2003.11.04 |
申请号 |
US20010016214 |
申请日期 |
2001.12.06 |
申请人 |
SYNPLICITY, INC. |
发明人 |
BORKOVIC DRAZEN;MCELVAIN KENNETH S. |
分类号 |
G06F17/50;H03K5/135;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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