| 摘要 |
What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write operations in the present integrated memory, in each case at least two word lines are activated simultaneously, in each case only one bit line being selected simultaneously. Compared with conventional memory architectures, this results in a high data rate even at very high frequencies and with a variable burst length, and additionally in a comparatively low power loss.
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