| 摘要 |
A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned "H" level, an NMOS 61-1 is turned off and a virtual ground line VGND1 is turned into floating state. When the signal RE is "H" level, the output level of an AND circuit 64-2 turns "L" level and NMOS 55a and 55b turn off. NMOS 53 and 54 turn on by "H" level of a word line WL2 and data in a bit line pair BL1 and BL/ is held on nodes N11 and N12. In reading out data, the signal RE is turned "L" level. When the NMOS 61-1 turns on and the VGND 1 becomes connected to GND, an acceleration circuit 55 accelerates the speed of readout operation.
|
