SYNCHRONOUS MEMORY DEVICE

摘要

PURPOSE: A synchronous memory device is provided to reduce timing of a column address path by removing time taken in repair judgement in the synchronous memory device having an additive latency(AL) mode. CONSTITUTION: A column address control unit(800) outputs the first column control pulse at a timing prior to a clock timing executing an operation according to an input command, and outputs the second column control pulse at a clock timing executing the operation according to the above command. A column address input unit(1000) converts an inputted column address into a column address synchronized according to an internal clock, and outputs it in response to the first column control pulse. A repair processing unit(3000) judges whether to repair a unit cell corresponding to the column address being output from the column address input unit, and outputs a decoding enable signal in response to the second column control pulse. And a column decoding unit(2000) decodes the column address being output from the column address input unit by being enabled according to the decoding enable signal.