| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that the amplitude of a limit cycle signal is large and the jitter dependence of feedback group characteristics is also large in conventional data receiving circuits (clock restoring circuits). <P>SOLUTION: The clock restoring circuit comprises a boundary detecting circuit 202 for detecting a boundary of an input signal in response to a first signal CLKb, and controls a timing of the first signal according to the detected boundary to conduct clock restoration. The clock restoring circuit is configured to have boundary detection timing varying means 207 and 208 for giving a variation portion to the first signal to vary dynamically a boundary detection timing in the boundary detecting circuit, and a variation reducing means 209 for reducing phase variation occurred at a restored clock, according to dynamic change of the boundary detection timing varied by the boundary detection timing varying means. <P>COPYRIGHT: (C)2004,JPO |
