SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR DESIGNING THE CIRCUIT, AND METHOD FOR INSPECTING DELAY FAILURE OF THE CIRCUIT

摘要

PROBLEM TO BE SOLVED: To appropriately inspect a delay failure in a short time without increasing a circuit size even when a plurality of paths are not detectable, when a pseudo random number generator 301 and an output response compressor 302 are integrated with a semiconductor integrated circuit having a plurality of scan flip-flops 316 to 322 constituting a scan path and a combination logical circuit 500 so as to allow self inspection of a delay failure due to an initialized test pattern and a final test pattern. SOLUTION: The semiconductor integrated circuit is provided with an inverter circuit 330 that analyzes timing on a net list, extracts a delay failure undetectable path, and inverts an input signal input into a normal signal input terminal D of the scan FF 320 at a starting point of the path. COPYRIGHT: (C)2004,JPO