发明名称 |
SEMICONDUCTOR INSPECTION DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, INSPECTION METHOD AND MANUFACTURING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To greatly reduce testing cost by collectively testing a plurality of semiconductor integrated circuit devices with a high precision. SOLUTION: A memory test device 1 is provided with a signature 5 as a random number generating circuit. Similarly, a test device DUT is provided with a signature circuit. At a time of testing, a plurality of test devices DUT is connected with an interface circuit 2 of the memory test device 1. A signature value generated by the signature circuit based on a response waveform output from an internal circuit of the test device DUT, and a signature value generated by the signature circuit 5 of the memory device 1 based on an expected value are compared with each other so as to determine capability of the plurality of test devices DUT connected to the interface circuit 2. COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2003307545(A) |
申请公布日期 |
2003.10.31 |
申请号 |
JP20020111735 |
申请日期 |
2002.04.15 |
申请人 |
HITACHI LTD |
发明人 |
KIKUCHI SHUJI;TOBA TADANOBU;HIRANO KATSUNORI;SONODA YUJI;WADA TAKESHI |
分类号 |
G01R31/28;G01R31/3181;G01R31/3183;G01R31/3185;G01R31/319;G01R31/3193;H01L21/66;H01L21/822;H01L27/04;(IPC1-7):G01R31/28;G01R31/318 |
主分类号 |
G01R31/28 |
代理机构 |
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主权项 |
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地址 |
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