发明名称 HDTV TRELLIS DECODER ARCHITECTURE
摘要 A trellis decoding system (1) for use in processing a High Definition Television signal. The trellis decoding system processes video data in the form of groups of interleaved trellis encoded data packets and includes a traceback unit (33) that identifies a sequence of antecedent trellis states in accordance with a state transition trellis. The delay, re-encoder and trellis demapper elements of previous trellis decoders are eliminated. A branch metric computer (2) includes eight discrete subunits (3), one for each possible trellis state. Each subunit (3) generates two output bits (14, 15) indicative of the two trellis branches exiting the trellis state represented by that particular subunit (3). An add-compare-select unit (8) includes eight discrete subunits (23), each associated with a particular trellis state. Each subunit (23) includes as an input two bits (28, 29) received from the branch metric computer (2) and as an output two bits (6, 31). Bit (31) is chosen from (28) and (29). Bit (6) is chosen from the branch metric information (26, 27) input to each subunit (23). A traceback control and memory unit (33) includes an N to 1 multiplexer (49) which receives as an input the output bits (6, 31) from the add-compare-select unit (8). The present system offers a hardware reduction from prior art.
申请公布号 WO03090451(A2) 申请公布日期 2003.10.30
申请号 WO2003US09862 申请日期 2003.04.01
申请人 THOMSON LICENSING S.A.;MARKMAN, IVONETE 发明人 MARKMAN, IVONETE
分类号 H03M13/41;H03M13/27;H03M13/29;H04L5/12;H04N5/00;H04N7/24 主分类号 H03M13/41
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