发明名称 Gate-coupled MOSFET ESD protection circuit
摘要 A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.
申请公布号 US2003201457(A1) 申请公布日期 2003.10.30
申请号 US20020320201 申请日期 2002.12.16
申请人 LIN SHI-TRON;CHEN WEI-FAN 发明人 LIN SHI-TRON;CHEN WEI-FAN
分类号 H01L23/62;H01L27/02;H01L29/74;H02H9/00;(IPC1-7):H01L29/74 主分类号 H01L23/62
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