| 摘要 |
The invention relates to a semiconductor component comprising an insulation layer, which is configured on the semiconductor substrate and in which a capacitor structure is formed (K). Said capacitor structure (K) comprises at least two parallel metallization planes (1, 2, 3, 6, 8), whereby at least one of said planes (1, 2, 3, 6, 8) is configured in a lattice and inhomogenous structures (1a to 1l; 10a, 10b), which are electrically connected to the first metallization plane (1, 2, 3, 6, 8), extend at least partially into the cavities of the latticework metallization plane (1, 2, 3, 6, 8). |
