| 摘要 |
A method and apparatus for executing a Viterbi decoding routine, in which the routine (input) is mapped to an array of interconnected reconfigurable processing elements (D). The processing elements function in parallel, and pass results to other processing elements to reduce the number of processing steps for executing the Viterbi decoding routine. Accordingly, the present invention may be used to perform the decoding routine with any number of constraint lengths and code rates, and be independent of a specific communication standard. Further, the present invention reduces power consumption and area in the use of circuits for performing the coding routine. |
