发明名称 Packet transfer apparatus, scheduler, data transfer apparatus, and packet transfer method
摘要 A packet transfer apparatus, a scheduler, a data transfer apparatus, and a packet transfer method which can control a transfer rate for each attribute according to an operational situation. When a packet is input, the buffer control circuit determines an attribute of the packet. The input packet is stored by the buffer control circuit in a buffer area which is associated with the determined attribute in advance. Thereafter, when it becomes possible to transmit a packet, the selector refers to information set in a register, and selects a buffer area which has a highest priority among at least one buffer area storing at least one packet. The selection result is sent to the buffer control circuit. Then, buffer control circuit outputs a packet stored in the selected buffer area.
申请公布号 US2003202525(A1) 申请公布日期 2003.10.30
申请号 US20030342252 申请日期 2003.01.15
申请人 FUJITSU LIMITED 发明人 NAGATOMO TERUHIKO
分类号 H04L12/56;(IPC1-7):H04L12/56 主分类号 H04L12/56
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