发明名称 System for control of pre-charge levels in a memory device
摘要 System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.
申请公布号 US2003202411(A1) 申请公布日期 2003.10.30
申请号 US20020136034 申请日期 2002.04.29
申请人 YAMADA SHIGEKAZU 发明人 YAMADA SHIGEKAZU
分类号 G11C16/06;G11C7/12;G11C16/02;(IPC1-7):G11C7/00 主分类号 G11C16/06
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