发明名称 Unified apparatus and method to assure probe card-to-wafer parallelism in semiconductor automatic wafer test, probe card measurement systems, and probe card manufacturing
摘要 A planarization gauge assures probe card-to-wafer parallelism in semiconductor automatic test equipment (ATE) used for wafer test, and provides a standard system reference plane during the building and testing of ATE components. The planarization gauge has two planar and parallel surfaces that may serve as a system reference plane The planarization gauge has at least one access hole for a depth gauge, and at least one optical target recognizable by a prober's upward looking camera. The planarization gauge is mechanically interchangeable with a probe card; thus, it is compatible with different planarization methods and platforms used in building and testing ATE components. The planarization gauge is manufactured and inspected in a manner as to assure traceability to established standards such as NIST. When used by all ATE vendors, the planarization gauge ensures correlation between the vendors' various planarization methods.
申请公布号 US2003201764(A1) 申请公布日期 2003.10.30
申请号 US20020133165 申请日期 2002.04.26
申请人 JAFARI NASSER ALI;KARKLIN KENNETH DEAN;SPRAGUE WILLIAM T. 发明人 JAFARI NASSER ALI;KARKLIN KENNETH DEAN;SPRAGUE WILLIAM T.
分类号 G01R1/06;G01R31/28;H01L21/66;(IPC1-7):G01R1/00 主分类号 G01R1/06
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