Architecture for multi-queue storage element

摘要

A circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.