ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

摘要

A device for protecting an integrated circuit (IC) against electrostatic dis charge (ESD) includes a self-triggered silicon controlle d rectifier (STSCR) coupled across the internal supply potentials (Vcc, Vss) o f the integrated circuit. The STSCR exhibits a snap-bac k in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR (30) is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes an n-well disposed in a p-substrate. A first n+ region (62) and p-type region (64) ar e both disposed in the n-well (60). The n+ and p-type r egions are spaced apart and electrically connected to form the anode of the SCR. The ESD protection device also includes diode clamps (26 , 27) between the periphery and internal power supply lines, and a novel well resi stor which provides a distributed resistance further pro tecting sensitive output buffer circuitry.