发明名称
摘要 A test circuit for integrated circuit devices shortens test times, and reduces the length of the test pattern and the number of external terminals. The test circuit is provided between first and second target circuits, and incorporates a first selection section for selecting one of a first output signal from the first target circuit, a second output signal from the second target circuit, and a test signal indicating a test pattern input via a test pattern input terminal. A temporarily data storage section stores the signal selected by the first section, and a second selection selects one of temporarily stored data or the second output signal. The results are provide to the first target circuit. A third selecting section is provided; for selecting one of the temporarily stored data signal or the first output signal, and providing the selected signal to the second target circuit.
申请公布号 JP3459799(B2) 申请公布日期 2003.10.27
申请号 JP19990297453 申请日期 1999.10.19
申请人 发明人
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22 主分类号 G01R31/28
代理机构 代理人
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