| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of not generating any power-on reset signal in recovery from a power saving mode based on a DPD signal, but generating a power-on reset signal even when a rising time is shortened. <P>SOLUTION: This power-on reset circuit is provided with a power saving mode falling delay circuit 1 for delaying the end timing of a power saving mode instruction, an OR logic reset output suppressing circuit 2 for not outputting any signal even when an edge signal is generated by an edge signal generating circuit N1 while a delayed power saving mode instruction DLPDP from the power saving mode falling delay circuit 1 is inputted, and a recovery accelerating circuit 3 equipped with a transistor N2 to be controlled by the output of the power saving mode falling delay circuit 1 for quickening the restoration of the edge signal, and disposed in parallel with a first voltage dividing resistance R1. The transistor N2 of the recovery accelerating circuit 3 is formed as an NMOS (N channel Metal Oxide Semiconductor) type FET (Field Effect Transistor). <P>COPYRIGHT: (C)2004,JPO</p> |
