| 摘要 |
PROBLEM TO BE SOLVED: To improve the planarity of a semiconductor device using a substitution gate process, and to increase its reliability. SOLUTION: A shallow groove element isolation region 402, an n-type transistor region 409, and a p-type transistor region 416 are formed on a silicon substrate 401. Dummy gate insulating films 403 and dummy gate electrodes 404 are formed on the regions. Sidewall spacers 405 are formed on the sidewalls. A silicon nitride film 407 and an interlayer film 408 are formed on the silicon substrate 401. The films (408, 407) are polished by CMP, until the upper surface of the dummy gate electrode 404 is exposed. The dummy gate electrode 404 and the dummy gate insulating film 403 of the n-type transistor region 409 are removed. The gate insulating film, having a high dielectric constant and a gate electrode material, is embedded between the sidewall spacers 405 of the n-type transistor region 409. COPYRIGHT: (C)2004,JPO
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