| 摘要 |
PROBLEM TO BE SOLVED: To enhance wiring operability by laying out low-cell-utilization-rate logic circuits so that wiring delay is reduced. SOLUTION: A logic circuit merging means 110 reads a cell placement region 210, a logic circuit 220, and multiple logic circuits 230 for raising a cell usage rate, and merges the logic circuit 220 and the multiple logic circuits 230 for raising the cell usage rate into one logic circuit 240 on the basis of the number of cells which can be placed in the cell placement region, then outputs a merged logic circuit 240. A primitive placement means 120 inputs the logic circuit 240, and places the primitive cell of the input logic circuit 240 on an LSI chip, then outputs the primitive placement result 250 of the logic circuit 240. A logic circuit deleting means 130 for raising the cell usage rate inputs the primitive placement result 250, and deletes the primitive placement result of the logic circuit 230 for raising the cell usage rate, which was merged through the logic circuit merging means 110, from input layout data, when outputs the primitive placement result 260 of the logic circuit 220. COPYRIGHT: (C)2004,JPO
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