发明名称 |
NON-UNIFORM CACHE APPARATUS, SYSTEMS, AND METHODS |
摘要 |
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
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申请公布号 |
WO03088048(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
WO2003US10621 |
申请日期 |
2003.04.08 |
申请人 |
UNIVERSITY OF TEXAS SYSTEM;BURGER, DOUG;KECKLER, STEPHEN, W.;KIM, CHANGKYU |
发明人 |
BURGER, DOUG;KECKLER, STEPHEN, W.;KIM, CHANGKYU |
分类号 |
G06F12/00;G06F12/08;G06F12/12;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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