发明名称 |
Digitale Phasenanpassung und integrierter Mehrkanalsender/empfänger, der diese benutzt |
摘要 |
A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented. <IMAGE> |
申请公布号 |
DE69433157(D1) |
申请公布日期 |
2003.10.23 |
申请号 |
DE1994633157 |
申请日期 |
1994.10.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP., ARMONK |
发明人 |
GEORGIOU, CHRISTOS JOHN;LARSEN, THOR ARNE;LI, KI WON |
分类号 |
H03M9/00;H04L7/033;(IPC1-7):H04L7/033 |
主分类号 |
H03M9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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