发明名称 Clock adjusting method and circuit device
摘要 A clock adjusting method adjusts a first clock supplied to a first flip-flop which is coupled to an output of a first circuit and a second clock supplied to a second flip-flop which is coupled to an input of a second circuit, where the first and second flip-flops are coupled via a transmission path. The clock adjusting method includes the steps of (a) transmitting data from the first flip-flop to the second flip-flop via the transmission path while varying delay quantities of the first and second clocks, (b) obtaining a combination of the delay quantities of the first and second clocks with which the data is correctly transmitted from the first flip-flop to the second flip-flop, and (c) adjusting the delay quantity of at least one of the first and second clocks based on the combination so as to synchronize operations of the first and second flip-flops.
申请公布号 US2003200496(A1) 申请公布日期 2003.10.23
申请号 US20030460393 申请日期 2003.06.13
申请人 FUJITSU LIMITED 发明人 YAMADA JUN
分类号 G06F1/10;G06F1/12;H03K5/13;H04L7/00;(IPC1-7):G06F11/00;G01R31/28 主分类号 G06F1/10
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