发明名称 |
Master-slave latch circuit for multithreaded processing |
摘要 |
A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in multiple modes, including a scan mode for testing purposes.
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申请公布号 |
US2003200424(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20030459646 |
申请日期 |
2003.06.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AIPPERSPACH ANTHONY GUS;ALFERNESS MERWIN HERSCHER;UHLMANN GREGORY JOHN |
分类号 |
G06F9/30;G06F9/38;G06F9/44;(IPC1-7):G06F9/44 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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