发明名称 |
Clock recovery circuit and data receiving circuit |
摘要 |
A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.
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申请公布号 |
US2003198105(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20030405370 |
申请日期 |
2003.04.03 |
申请人 |
FUJITSU LIMITED |
发明人 |
YAMAGUCHI HISAKATSU;TAMURA HIROTAKA |
分类号 |
G11C7/10;H03L7/091;H04L7/033;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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