| 摘要 |
A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit (54) and providing a second clock signal to a memory (52) storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal. The other clock is synchronized to said first or second clock. The synchronization circuit can be selectively place in a first operational mode, to synchronize the first clock to the reference clock or in a second operational mode, to synchronize the second clock to the reference clock.
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